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PD - 94089D
IP2001
Synchronous Buck Multiphase Optimized BGA Power Block
Integrated Power Semiconductors, Drivers & Passives
Features:
* * * * *
20A continuous output current with no derating up to TPCB = 90C Very small 11mm x 11mm x 3mm profile Internal features minimize layout sensitivity * Optimized for very low power losses 3.3 to 12V input voltage IP2001 Power Block
Description The IP2001 is a fully optimized solution for high current synchronous buck multiphase applications. Board space and design time are greatly reduced because most of the components required for each phase of a typical discrete-based multiphase circuit are integrated into a single 11mm x 11mm x 3mm BGA power block. The only additional components required for a complete multiphase converter are a PWM IC, the external inductors, and the input and output capacitors. iPOWIR technology offers designers an innovative board space saving solution for applications requiring high power densities. iPOWIR technology eases design for applications where component integration offers benefits in performance and functionality. iPOWIR technology solutions are also optimized internally for layout, heat transfer and component selection.
IP2001 Internal Block Diagram
VIN PRDY ENABLE PWM VDD MOSFET Driver with dead time control
VSW
SGND
PGND
* All of the difficult PCB layout and bypassing issues have been addressed with the internal design of the iPOWIR Block. There are no concerns about double pulsing, unwanted shutdown, or other malfunctions which often occur in switching power supplies. The iPOWIR Block will function normally without any additional input power supply bypass capacitors. However, for reliable long term operation it is recommended that the adequate amount of input decoupling is provided on the VIN pin. No additional bypassing is required on the VDD pin.
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04/26/02
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IP2001
Parameter VIN to PGND Output RMS Current VDD to SGND DRV_IN to SGND Enable to SGND Storage Temperature
All specifications @ 25C (unless otherwise specified)
Absolute Maximum Ratings : Min -0.3 -0.3 -40 Typ Max 16 20 6.0 6.0 6.0 125 Units V A V V V C Conditions
Recommended Operating Conditions : Parameter Supply Voltage Input Voltage Range Output Voltage Range Output Current Range Operating Frequency Symbol VDD VIN VOUT IOUT fsw Min 4.6 3.0 0.9 150 Typ 5.0 Max 5.5 12.6 3.3 20 1000 Units V V V A kHz
see Figs. 2 & 4 see Fig. 2 see Figs. 2 & 5
Conditions
Electrical Specifications @ VDD = 5V (unless otherwise specified) : Parameter Block Power Loss Turn On Delay Turn Off Delay VIN Quiescent Current VDD Quiescent Current Under Voltage Lockout Start Threshold Hysteresis Enable Input Voltage High Input Voltage Low Power Ready Logic Level High Logic Level Low Drive Input Logic Level High Logic Level Low Symbol PBLK td(on) td(off) IQ-VIN IQ-VDD UVLO VSTART VHys-UVLO Enable VIH VIL PRDY VOH VOL DRV_IN VOH VOL Min 4.2 2.0 4.5 2.0 Typ 3.1 63 26 4.4 .05 4.6 0.1 Max 3.8 1.0 10 4.5 0.8 0.2 0.8 Units W ns mA A V Conditions
VIN = 12V, VOUT = 1.6V, IOUT = 20A, fSW = 500kHz
Enable = 0V, VIN = 12V Enable = 0V, VDD = 5V
V
V
VDD = 4.6V, ILoad = 10mA VDD < UVLO Threshold, ILoad = 10A
V
Measurement were made using four 10uF (TDK C3225X7R1C106M or equiv.) capacitors across the input (see Fig. 8). Not associated with the rise and fall times. Does not affect Power Loss (see Fig. 9).
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IP2001
Pin Description Table
Pin Name VDD VIN
PGND
VSW
SGND
Ball Designator A1 - A3, B1 - B3 A5 - A12, B5 - B12, C5 - C10 C11, C12, D11, D12, E11, E12, F6, F7, F12, G6, G7, G12, H6, H7, H12, J6, J7, J12, K5 - K7, K12, L5, L6, L12, M5 - M7, M12 D5 - D10, E5 - E10, F8 - F11, G8 - G11, H8 - H11, J8 - J11, K8 - K11, L8 - L11, M8 - M11 C1 - C3, D1 -D3, E1 -E3
Pin Function
Supply voltage for the internal circuitry. Input voltage for the DC-DC converter.
Power Ground - connection to the ground of bulk and filter capacitors.
Switching Node - connection to the output inductor.
ENABLE
F1
PRDY
K1
PWM NC
H1 B4, C4, D4, E4, F2 - F4, G2 - This pin is not for electrical connection. It G4, H2 - H4, J1, J2 - J4, K3, should be attached only to dead copper. L1, L2, M1 - M4
Signal Ground. When set to logic level high, internal circuitry of the device is enabled. When set to logic level low, the PRDY pin is forced low, the Control and Sychronous switches are turned off, and the supply current is less than 10A. Power Ready - This pin indicates the status of VDD. When VDD is less than 4.4V(typ.), this output is driven low. When VDD is greater than 4.4V(typ.), this output is driven high. This output has a 10mA source and 10A sink capability. TTL-level input signal to MOSFET drivers.
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IP2001
5.0
22 20
4.5
4.0
3.5
VIN = 12V VOUT = 1.6V TBLK = 125C fSW = 500kHz Maximum Typical
Output Current (A)
18 16 14 12 10 8 6
Power Loss (W)
3.0
2.5
Safe Operating Area
VIN = 12V VOUT = 1.6V fSW = 500kHz
2.0
1.5
1.0
4 2 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
0.5
0.0
0
10
20
30
40
50
60
70
80
90
100
110
120
130
Output Current (A)
PCB Temperature (C)
Fig 1. Power Loss vs. Current
Fig 2. Safe Operating Area (SOA) vs. TPCB*
(*see AN-1030 for details)
Adjusting the Power Loss and SOA curves for different operating conditions
To make adjustments to the power loss curves in Fig. 1, multiply the normalized value obtained from the curves in Figs. 3, 4, 5 or 6 by the value indicated on the power loss curve in Fig. 1. If multiple adjustments are required, multiply all of the normalized values together, then multiply that product by the value indicated on the power loss curve in Fig. 1. The resulting product is the final power loss based on all factors. To make adjustments to the SOA curve in Fig. 2, determine the maximum allowed PCB temperature in Fig. 2 at the required operating current. Then, add the correction temperature from the normalized curves in Figs. 3, 4, 5 or 6 to find the final maximum allowable PCB temperature. When multiple adjustments are required, add all of the temperatures together, then add the sum to the PCB temperature indicated on the SOA graph to determine the final maximum allowable PCB temperature based on all factors. Operating Conditions for the examples below: Output Current = 20A Output Voltage = 2.5V Adjusting for Maximum Power Loss: (Fig. 1) (Fig. 3) (Fig. 4) (Fig. 5) Maximum power loss = 5W Normalized power loss for input voltage 0.925 Normalized power loss for output voltage 1.1 Normalized power loss for frequency 1.225 Adjusted Power Loss = 5W x 1.1 x 0.925 x 1.225 6.23W Adjusting for SOA Temperature: (Fig. 2) (Fig. 3) (Fig. 4) (Fig. 5) SOA PCB Temperature = 90C Normalized SOA PCB Temperature for input voltage 2.6C Normalized SOA PCB Temperature for output voltage -3.5C Normalized SOA PCB Temperature for frequency -7.5C Adjusted SOA PCB Temperature = 90C - 3.5C + 2.6C - 7.5 81.6C Input Voltage = 7V Sw Freq= 750kHz
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IP2001
Typical Performance Curves
1.02 1.01 1.00 -0.7
1.20
-7.0
Power Loss (Normalized)
Power Loss (Normalized)
0.99 0.98 0.97 0.96 0.95 0.94 0.93 0.92 3 5
VOUT = 1.6V IOUT = 20A fSW = 500kHz TBLK = 125C
-0.4 0.0 0.4 0.7 1.1 1.4 1.8 2.1 2.5 2.8
1.16
1.12
VIN = 12V IOUT = 20A fSW = 500kHz TBLK = 125C
SOA PCB Temperature Adjustment (C)
-5.6
SOA PCB Temperature Adjustment (C)
-4.2
1.08
-2.8
1.04
-1.4
1.00
0.0
0.96
1.4
0.92 0.9 1.3 1.7 2.1 2.5 2.9 3.3
2.8
7
9
11
13
Input Voltage (V)
Output Voltage (V)
Fig 3. Normalized Power Loss vs. VIN
1.5 -17.5
Fig 4. Normalized Power Loss vs. VOUT
1.5 -17
1.4
Power Loss (Normalized)
Power Loss (Normalized)
1.3
VIN = 12V VOUT = 1.6V IOUT = 20A TBLK = 125C
-14.0
1.4
-10.5
1.3
1.2
-7.0
VIN = 12V VOUT = 1.6V IOUT = 20A fSW = 500kHz TBLK = 125C
SOA Board Temperature Adjustment (C)
-14
SOA Temperature Adjustment (C)
-10
1.1
-3.5
1.2
-7
1.0
0.0
1.1
-4
0.9
3.5
1.0
0
0.8
7.0
0.7 100
250
500
750
10.5 1000
0.9 0 5 10 15 20 25
3
Switchin Frequency (kHz)
Peak to Peak Inductor Ripple Current (A)
Fig 5. Normalized Power Loss vs. Frequency
80 70
Fig 6. Normalized Power Loss vs. Ripple Current
Average Current (mA)
60 50 40 30 20 10 0 0 200 400 600 800 1000
Does not include PRDY current
Switching Frequency (kHz)
Fig 7. IDD vs. Frequency www.irf.com 5
12
11
10
9
8
7
1
2
3
4
5
6
U1 FB VCC 10K +5V U3 Vin C6 10uF SWNODE2 ENABLE2 D2 PRDY2 11 17 18 R13 0 +5V VDD3 VIN3 C9 10uF C10 10uF 10uF SWNODE3 ENABLE3 D3 PRDY3 PGND3 VSW3 C11 C31 10uF SGND3 PWM3 R17 10K ENABLE Vin U4 IP2001 R12 0 PGND2 0.54uH C18 Open C19 Open C20 100uF VSW2 L2 C7 10uF C8 10uF C30 10uF R7 2K 1% TP7 SWNODE2 VIN2 ISEN1 PWM1 0 13 SGND2 R11 0 PWM2 ENABLE R16 10K 14 ISEN2 PWM2 15 R10 IP2001 VDD2 16 20 C2 10uF R19 COMP 10 VSEN PGOOD VID4 VID3 VID2 VID1 VID0 FS/DIS GND HIP6311 PWM4 ISEN4 PWM3 ISEN3 12 19 1 2 3 4 5 8 9
7
6
6
IP2001
S1 SW-DIP6A Vin C3 10uF SWNODE1 ENABLE1 D1 0.54uH PRDY1 C15 Open C16 Open C17 100uF PGND1 VSW1 L1 VOUT C4 10uF C5 10uF C29 10uF
*Rx &Cx are not parts of PCB
R3 open +5V C28 22pF R1 1k 0.022uF open R14 ENABLE C1 PWM1 +5V R15 10K SGND1 R5 2K 1% TP6 SWNODE1 VIN1 IP2001 VDD1 U2 TP18 Vin
Rx Cx
51 4700pF R2 1K
ENABLE
R6 10K
+5V
VOUT SENSE
TP5
VID4 PGOOD
VID3
VID2 VID1 VID0
TP10 VOUT TP11 VOUT TP12 VOUT TP13 VOUT VOUT SENSENE TP21 C33 VOUT SENSE 0.01uF X7R PGNDSENSE TP22 PGND SENSE
Freq. Set Resistor
R4 51K
R8 2K 1% TP8 SWNODE3 L3 0.54uH C21 Open C22 Open C23 100uF
TP19 +5V
+5V
TP14 PGND TP15 PGND TP16 PGND TP17 PGND
C27
10uF +5V VIN4 C12 10uF SWNODE4 ENABLE4 D4 PRDY4 PGND4 VSW4 C13 10uF C14 10uF C32 10uF U5 Vin R9 2K 1% TP9 SWNODE4 L4 0.54uH C24 Open C25 Open C26 100uF
TP20 IP2001 VDD4 SGND4 PWM4 R18 10K ENABLE
PGND
4-Phase Reference Design Schematic
Screw hex4-40 used to generate BOM only HN2 HN1
*
Note: Rx and Cx are add on components
Stand off
ST1
ST2
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IP2001
Designator
C1 C2-C14, C27, C29-C32 C15, C16, C18, C19, C21, C22, C24, C25 C17, C20, C23, C26 C28 C33 Cx D1 - D4 L1 - L4 R1 & R2 R3 & R14 R4 R5, R7, R8, R9 R6, R15 - R19 R10 - R13 Rx S1 ST1 - ST4 U1 U2 - U5
Value 1 Value 2
.022uF 10uF 100uF 22pF 0.01uF 4700pF 30V 0.54uH 1K 51K 2K 10K 0 51 SPST Stand Off 4.6-6 V 50V 16V 6.3V 50V 50V 50V 100mA 27A 1/8W 1/8W 1/8W 1/8W 1/8W 1/10W 6 position 0-1.850V -
Type
X7R X5R X5R NPO X7R X7R Schottky Ferrite Thick film Thick film Thick film Thick film Thick film Thick film DIP PWM IC -
Tolerance Package
10% 10% 10% 5% 10% 10% 20% 5% 5% 1% 5% <50m 5% 0 - 70C 0805 1210 2220 0805 0805 0603 SOT23 SMT 0805 0805 0805 0805 0805 0603 SMT 4-40 20 Ld SOIC 11x11mm
Mfr. 1
ROHM TDK TDK TDK TDK Phicomp Central Panasonic ROHM ROHM KOA ROHM ROHM KOA C&K Comp. Keystone Intersil IR
Mfr. 1 Part No.
MCR215C223KK C3225X5R1C106KT C5750X5R0J107KT C2012X7R1H220JT C2012X7R1H103KT 06032R472K9B20 CMPSH-3 ETQP6F0R6BFA MCR10EZHJ102 MCR10EZHJW513 RK73H2A2001F MCR10EZHJ103 MCR10EZHJ000 RM73B1J510J SD06H0SK 8412K HIP6311CB IP2001
Mfr. 2
Murata MuRata ROHM SAMSUNG Bi Technologies -
Mfr. 2 Part No.
GRM42-2 X5R 106K16 GRM44-1-X5R 107K 6.3 MCH215A220JK CL21B103KBNC HM73-30R60 -
4-Phase Reference Design Bill of Materials
90%
PIN = VIN Average x IIN Average PDD = VDD Average x IDD Average POUT = VOUT Average x IOUT Average PLOSS = (PIN + PDD) - POUT
PRDY Average VDD Current A Average VDD Voltage V
DC
Average Input Current A
DC
V
Average Input Voltage
PWM
10%
VIN
ENABLE PWM VDD SGND PGND VSW
Average Output Current A
90%
IP2001
Averaging Circuit V
VSW
Average Output Voltage
10%
td(on)
td(off)
Fig 8. Power Loss Test Circuit
Fig 9. Timing Diagram
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IP2001
VDD
NC NC
VIN
SGND
NC NC
PGND
ENABLE
NC NC
PWM
NC NC NC NC NC PGND
VSW
NC
PRDY
NC
NC
Dimensions shown in inches (millimeters)
Recommended PCB Footprint (Top View)
8 www.irf.com
IP2001
0.15 [.006] C 2X 6 11.00 [.433] B A 5 C 0.45 [.0177] 0.35 [.0138] 0.12 [.005] C BALL A1 CORNER ID 11.00 [.433] NOTES: 1. 2. 3. 4. 5 6 7 DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES]. CONTROLLING DIMENSION: MILLIMETER SOLDER BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. PRIMARY DATUM C (SEATING PLANE) IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. BILATERAL TOLERANCE ZONE IS APPLIED TO EACH SIDE OF THE PACKAGE BODY. SOLDER BALL DIAMETER IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, IN A PLANE PARALLEL TO DATUM C.
0.15 [.006] C TOP VIEW 2X 6
133X O
0.55 [.0216] 0.45 [.0178]
7 CAB C
0.15 [.006] 0.08 [.003]
0.40 [.016] 4X BOTTOM VIEW
0.80 [.032] 22X
(4X 1.1 [.043])
2.66 [.1047] 2.46 [.0969] 3.11 [.1224] 2.81 [.1107] SIDE VIEW
Mechanical Drawing
Refer to the following application notes for detailed guidelines and suggestions when implementing iP0WIR Technology products:
AN-1028: Recommended Design, Integration and Rework Guidelines for International Rectifier's iPOWIR Technology BGA Packages This paper discusses the assembly considerations that need to be taken when mounting iPOWIR BGA's on printed circuit boards. This includes soldering, pick and place, reflow, inspection, cleaning and reworking recommendations. AN-1029: Optimizing a PCB Layout for an iPOWIR Technology Design This paper describes how to optimize the PCB layout design for both thermal and electrical performance. This includes placement, routing, and via interconnect suggestions. AN-1030: Applying iPOWIR Products in Your Thermal Environment This paper explains how to use the Power Loss and SOA curves in the data sheet to validate if the operating conditions and thermal environment are within the Safe Operating Area of the iPOWIR product. www.irf.com 9
IP2001
0123 XXXX IP2001
Part Marking
0123 XXXX IP2001
0123 XXXX IP2001
24mm
16mm
FEED DIRECTION
Tape & Reel Information
Data and specifications subject to change without notice. This product has been designed and qualified for the industrial market. Qualification Standards can be found on IR's Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.8/01 10 www.irf.com

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